Digital Design and Computer Architecture

• Profs: O. Mutlu, S. Sadrosadati
• Website: https://safari.ethz.ch/ddca/spring2025/doku.php?id=start
• Moodle: https://moodle-app2.let.ethz.ch/course/view.php?id=25002
• Admin: Admin
• Videos: 1) 2023: https://www.youtube.com/playlist?list=PL5Q2soXY2Zi-EImKxYYY1SZuGiOAOBKaf 2) 2025: https://www.youtube.com/playlist?list=PL5Q2soXY2Zi9Eo29LMgKVcaydS7V1zZW3
• Cheatsheet: speedrun.pdf

I suggest reading the General Summary as it is much more content dense and to the point over the individual lecture notes.

This Digital Design and Computer Architecture course, taught by Prof Mutlu, provides a fascinating and comprehensive overview of how modern computers work from the ground up. It covers everything from fundamental logic gates and sequential circuits to complex microarchitectural concepts like pipelining, out-of-order execution, and memory hierarchies.

Professor Mutlu’s passion for the subject is undeniable; his enthusiasm is infectious and makes the lectures engaging. A major strength of the course was its connection to real-world challenges, as he frequently discussed current industry problems and future research directions.

However, the lectures themselves could have been more content-dense. They were often quite long and the slides felt repetitive, which sometimes made it difficult to focus on the key takeaways. The practical side of the course was also a mixed experience. While the lab sessions were nice, the tools and assignments felt somewhat outdated. The Vivado software, in particular, was cumbersome to install and operate, creating unnecessary friction.

Overall, this is a very interesting and important course that gives you a foundational understanding of computer architecture. While it could benefit from a modernization of its practical components, the depth of the material and Prof Mutlu’s passionate teaching make it a highly valuable learning experience.

Lecture Notes

• 01 Introduction and Basics
• 02 Tradeoffs, Metrics & Combinational Logic 1
• 03 Combinational Logic 2
• 04 Sequential Logic Design
• 04.5 Labs Intro and FPGAs
• 05 Sequential Logic Design II & Hardware Description Languages and Verilog
• 06 Hardware Description Languages and Verilog II, Timing
• 06.5 Verification & Testing
• 07 Von Neumann Model & Instruction Set Architectures
• 08 Instruction Set Architectures II
• 09 ISA & Microarchitecture
• 09.5 Assembly Programming
• 10 Microarchitecture Fundamentals and Design
• 11 Multi-Cycle Microarchitecture Design
• 12 Pipelining, Data Dependencies
• 13 Pipelined Processor Design - Data & Control Dependence Handling
• 14 Precise Exceptions & Register Renaming
• 15 Out-of-Order Execution
• 15.5 Load-Store Handling in Out-of-Order Execution
• 16 Superscalar Execution & Branch Prediction
• 17 Advanced Branch Prediction
• 18 VLIW and Systolic Array Architectures
• 18.5 Decoupled Access-Execute
• 19 SIMD Architectures (Vector and Array Processors)
• 20 GPU Architectures
• 21 Memory Systems, DRAM
• 22 Memory Hierarchy, Caching, Direct-Mapped, Set-Associative, Fully Associative Caches
• 23 Cache Design and Management
• 24 Multicore Caching and Cache Coherence, Prefetching
• 25 Prefetching, RL based PF, Execution-Based PF, Virtual Memory
• 26 Virtual Memory, Multi-Table-VM, Translation-Lookaside-Buffer, Memory Protection

Study Notes

• General Summary
• Microarchitecture Concepts (Pipelining, OoO, Superscaler, VLIW, Systolic, SIMD etc, and GPUs) Summary

Other Stuff

• Useful Resources