Lecture from: 05.03.2023 | Video: YT
Introduction to Labs and FPGAs
This lecture introduces the lab component of the course, focusing on Field-Programmable Gate Arrays (FPGAs).
Lab Logistics
- Locations: On-site labs in designated rooms (HG E19, HG E26.1, etc.) and online Zoom meetings (details via Moodle).
- Schedule: Refer to the DDCA Course Catalogue Web Page for specific times.
- Grading: 10 labs, 30 points total. 70% in-class evaluation, 30% mandatory lab reports (1-point penalty for late submission). Labs should be finished within one week of announcement. Grades from past years can be used.
- Questions: Contact via email ([email protected]) or Moodle forum.
What We Will Learn in the Labs
- Trade-offs: Understanding the balance between performance and area/complexity in hardware implementations.
- Hands-on Experience:
- Hardware prototyping on FPGAs.
- Debugging hardware implementations.
- Hardware Description Language (HDL) - Verilog.
- Hardware design flow.
- Computer-Aided Design (CAD) tools.
- Goal: build a 32-bit microprocessor.
What is an FPGA?
- Field-Programmable Gate Array (FPGA): A software-reconfigurable hardware substrate. It’s an integrated circuit that can be configured after manufacturing.
- Key Features:
- Reconfigurable Functions: Implements logic functions that can be changed.
- Reconfigurable Interconnection: Connections between functional units can be modified.
- Reconfigurable Input/Output (IO): Mapping of internal signals to physical pins can be adjusted.
FPGAs vs. Other Integrated Circuits
| Device Type | Flexibility/Programming Ease | Efficiency | Description |
|---|---|---|---|
| CPUs (Central Processing Units) | High | Low | General-purpose processors, easy to program but less efficient for specialized tasks. |
| GPUs (Graphics Processing Units) | Medium | Medium | Designed for parallel processing (especially graphics), more efficient than CPUs for certain tasks but less flexible than FPGAs. |
| FPGAs | Medium | Medium | Offer a balance between flexibility and efficiency. Harder to program than CPUs/GPUs but more efficient for specialized tasks. Easier to develop than ASICs. |
| ASICs (Application-Specific ICs) | Low | High | Custom-designed for a specific application, offering maximum efficiency but no flexibility. |
FPGAs in Today’s Systems (Examples)
- Microsoft’s Project Brainwave: Deep learning platform for real-time AI inference using FPGAs as Neural Processing Units (NPUs).
- Amazon EC2 F1 Instances: Cloud-hosted FPGAs for custom hardware acceleration.
- Genomics: Accelerating DNA sequencing and analysis (e.g., DRAGEN, GateKeeper, SneakySnake).
- Climate Modeling: Accelerating weather prediction models.
- DRAM/Flash Memory Testing: SoftMC and DRAM Bender, open-source FPGA-based infrastructures for memory research (RowHammer, etc.).
- Processing-in-Memory Prototyping: PiDRAM, an FPGA-based framework for exploring processing-in-DRAM architectures.
- Prototyping New Arch: MetaSys: A metadata management system.
Overview of Lab Exercises
The labs will culminate in building a 32-bit MIPS microprocessor on an FPGA.
- Lab 1: Drawing a Basic Circuit (Comparator): Implementing a simple comparison circuit (no FPGA programming yet).
- Lab 2: Mapping Your Circuit to FPGA (Adder): Building a 1-bit adder, then a 4-bit adder, and implementing it on the FPGA (switches for input, LEDs for output).
- Lab 3: Verilog for Combinatorial Circuits (Seven-Segment Display): Displaying the adder’s output on a seven-segment display.
- Lab 4: Finite State Machines (Blinking LEDs): Implementing sequential logic (memories) to create blinking LEDs (car turn signals).
- Lab 5: Implementing an ALU: Building an Arithmetic Logic Unit (ALU), a core component of a processor.
- Lab 6: Testing the ALU: Simulating and debugging the ALU design.
- Lab 7: Writing Assembly Code (MIPS): Writing MIPS assembly code for image manipulation, which will later run on the processor.
- Lab 8: Full System Integration: Building the complete MIPS processor.
- Lab 9: The Performance of MIPS: Improving processor performance by adding new instructions (multiplication, bit shifting).
FPGA Board (Basys 3)
- Components: microUSB (power/programming), video out (VGA), USB, power switch, seven-segment displays, LEDs, switches, push-buttons, FPGA chip.
FPGA Architecture: A Closer Look
- Main Building Blocks:
- Look-Up Tables (LUTs): Implement logic functions. A 3-LUT can implement any 3-input Boolean function. Modern FPGAs often use 6-LUTs.
- Switches: Connect LUTs and other components.
- Other Components: Interconnects, I/O blocks, configuration memory (stores the LUT configurations), flip-flops (for sequential logic).
- Modern FPGA: on-chip memory, hardware blocks.
Programming an FPGA
- LUT Programming: The configuration memory of a LUT is loaded with values that define the output for each possible input combination. It acts like a truth table implemented with a multiplexer.
- Complex Functions: Implemented by connecting multiple LUTs and switches.
- FPGA Design Flow:
- Problem Definition: Define the desired functionality.
- Hardware Description Language (HDL): Describe the circuit using Verilog (or VHDL).
- Logic Synthesis: Convert the HDL code into a netlist of logic gates.
- Placement and Routing: Map the logic gates to specific LUTs and switches on the FPGA, and determine the connections between them.
- Bitstream Generation: Create a configuration file (bitstream) that programs the FPGA.
Computer-Aided Design (CAD) Tools (Vivado)
- Vivado: A software suite from Xilinx (now AMD) that automates the FPGA design flow.
- Features:
- HDL editing and synthesis.
- Simulation and debugging.
- Placement and routing.
- Bitstream generation.
- Device programming (via USB).
- Availability: Installed in lab computers.
Continue here: 05 Sequential Logic Design II & Hardware Description Languages and Verilog