06 Hardware Description Languages and Verilog II, Timing

Lecture from: 10.03.2023 | Video: YT

This lecture note covers the continuation of Hardware Description Languages (HDLs) with Verilog, focusing on implementing sequential logic and elaborating on both structural and behavioral modeling.

Agenda for Today

• Hardware Description Languages
• Implementing Combinational Logic (in Verilog)
• Implementing Sequential Logic (in Verilog)

The Verilog slides are a tutorial and may not be fully covered in lecture, but all slides will be beneficial for your labs.

Recall

Why Specialized Languages for Hardware?

• HDLs enable easy description of hardware structures:
  • Wires, gates, registers, flip-flops, clock, rising/falling edge, etc.
  • Combinational and sequential logic elements.
• HDLs enable seamless expression of parallelism inherent in hardware:
  • All hardware logic operates concurrently.
• Both of the above ease specification, simulation, and synthesis.

Hardware Design Using HDL

This section delves into hardware design methodologies using HDLs, particularly Verilog.

Two Main Styles of HDL Implementation

• Structural (Gate-Level)
  • The module body contains a gate-level description of the circuit.
  • Describes how modules are interconnected.
  • Each module contains other modules (instances).
  • Describes a hierarchy of modules defined as gates.
• Behavioral
  • The module body contains a functional description of the circuit.
  • Contains logical and mathematical operators.
  • The level of abstraction is higher than gate-level.
    • Many possible gate-level realizations of a behavioral description.
• Many practical designs use a combination of both structural and behavioral styles.

What Happens with HDL Code?

• Synthesis (i.e., Hardware Synthesis)
  • Modern tools map synthesizable HDL code into low-level cell libraries → netlist describing gates and wires.
  • They perform many optimizations.
  • However, they cannot guarantee an optimal solution, mainly due to computationally expensive placement and routing algorithms.
  • It’s necessary to describe circuits in HDL in a way that is nice-to-synthesize, which is the most common way of Digital Design these days.
• Simulation
  • Allows the behavior of the circuit to be verified without actually manufacturing it.
  • Simulators can work on structural or behavioral HDL.
  • Simulation is essential for functional and timing verification.

Sequential Logic in Verilog

This section focuses on how to describe and implement sequential logic circuits using Verilog HDL.

Sequential Logic in Verilog

• We can describe hardware that has memory: Flip-Flops, Latches, Finite State Machines.
• Sequential Logic state transition is triggered by a “CLOCK” signal:
  • Latches are sensitive to the level of the signal.
  • Flip-flops are sensitive to the transitioning of the signal (edge-triggered).
• Combinational HDL constructs are not sufficient to express sequential logic.
  • We need new constructs: always and posedge/negedge.

The “always” Block

The always block is the fundamental construct in Verilog for describing sequential and some combinational logic.

always @ (sensitivity list)
  statement;

• always @ (...): Defines a procedural block that executes whenever an event in the sensitivity list occurs.
• sensitivity list: Specifies the signals or clock edges that trigger the block’s execution.
• statement: The Verilog code to be executed when triggered.

Example: D Flip-Flop (Verilog)

Verilog code to describe a D Flip-Flop using an always block.

module flop(input clk, input [3:0] d, output reg [3:0] q);
 
  always @ (posedge clk) // Sensitivity list: rising edge of clk
    q <= d;             // Non-blocking assignment: q gets d at clock edge
 
endmodule

• output reg [3:0] q;: Output q is declared as reg. Variables assigned in always blocks must be of type reg.
• always @ (posedge clk): The block is triggered only on the rising edge of the clk signal.
• q <= d;: Non-blocking assignment. q is updated with the value of d at the end of the clock edge event.

The keyword reg does not necessarily mean a physical register, but indicates a variable that can hold its value between assignments. assign statements are not used within always blocks. <= describes a non-blocking assignment.

Asynchronous and Synchronous Reset

Reset signals are essential for initializing sequential circuits to a known state.

• Reset Signals: Used to initialize hardware to a known state, typically at system start-up.
• Asynchronous Reset:
  • Reset signal is sampled independent of the clock.
  • Reset has the highest priority.
  • Sensitive to glitches, may have metastability issues.
• Synchronous Reset:
  • Reset signal is sampled with respect to the clock.
  • The reset should be active long enough to get sampled at the clock edge.
  • Results in a completely synchronous circuit.

D Flip-Flop with Asynchronous Reset

module flop_ar (input clk, input reset, input [3:0] d, output reg [3:0] q);
 
  always @ (posedge clk, negedge reset)
  begin
    if (reset == 0)   // Asynchronous reset condition (active low)
      q <= 0;       // Reset: force q to 0 immediately
    else
      q <= d;       // Normal operation: Load data d on rising clock edge
  end
 
endmodule

• always @ (posedge clk, negedge reset): Sensitivity list includes both rising edge of clk and falling edge of reset.
• if (reset == 0): If reset is low, q is reset asynchronously.
• else q <= d;: Otherwise, q is updated with d on the rising clock edge.

D Flip-Flop with Synchronous Reset

module flop_sr (input clk, input reset, input [3:0] d, output reg [3:0] q);
 
  always @ (posedge clk) // Sensitivity list: posedge clk only
  begin
    if (reset == '0')  // Synchronous reset condition (active low)
      q <= 0;         // Reset: force q to 0 synchronously with clock
    else
      q <= d;         // Normal operation: Load data d on rising clock edge
  end
 
endmodule

• always @ (posedge clk): Sensitivity list includes only the rising edge of clk.
• if (reset == '0'): Reset condition is checked synchronously at the clock edge.

D Flip-Flop with Enable and Reset

module flop_en_ar (input clk, input reset, input en, input [3:0] d, output reg [3:0] q);
 
  always @ (posedge clk, negedge reset)
  begin
    if (reset == '0')
      q <= 0;
    else if (en)       // Enable condition
      q <= d;
  end
 
endmodule

• input en;: Added an enable input en.
• else if (en): Data d is loaded into q only if reset is not asserted and en is high.

Example: D Latch (Verilog)

module latch (input clk, input [3:0] d, output reg [3:0] q);
 
  always @ (clk, d) // Sensitivity list: clk OR d (level-sensitive)
    if (clk)         // Latch is transparent when clk is high
      q <= d;
 
endmodule

• always @ (clk, d): Sensitivity list includes both clk and d for level-sensitive behavior.
• if (clk): Latch is transparent when clk is high.

Summary: Sequential Statements So Far

• Sequential statements are within an always block.
• The sequential block is triggered with a change in the sensitivity list.
• Signals assigned within an always block must be declared as reg.
• We use <= for (non-blocking) assignments and do not use assign within the always block.

Basics of always Blocks

• You can have as many always blocks as needed, but assignment to the same signal in different always blocks is not allowed.

Why Does an always Block Remember?

always blocks with edge-triggered sensitivity lists (like posedge clk) imply memory because the reg variable retains its value between triggering events.

An always Block Does NOT Always Remember

always blocks can also describe combinational logic if they are level-sensitive (e.g., always @ (*)) and assigned signals are updated continuously.

always Blocks for Combinational Circuits

An always block defines combinational logic if:

1. All outputs are always (continuously) updated.
2. All right-hand side signals are in the sensitivity list (use always @(*) for short).
3. All left-hand side signals get assigned in every possible condition of if..else and case blocks.

Be cautious of unintentionally describing memory elements (latches) when using always blocks for combinational logic.

Sequential or Combinational? - Examples

The always Block is NOT Always Practical/Nice

For simple combinational logic, assign statements are often more concise and readable than always blocks.

always Block for Case Statements (Handy!)

always blocks are particularly useful for complex combinational logic, especially with case statements for multi-way selections.

Summary: always Block (Combinational Logic)

• if...else and case statements can only be used inside always blocks.
• Combinational always Blocks are combinational only if all reg variables are always assigned.
• Use a default case in case statements to avoid unintended latches.
• Use casex statement to handle “don’t care” conditions.

Non-Blocking and Blocking Assignments

Verilog offers two types of assignments within always blocks: non-blocking (<=) and blocking (=).

• Non-Blocking Assignment (<=): Assignments are scheduled to happen at the end of the block, executed concurrently, and process flow is not-blocked.
• Blocking Assignment (=): Assignments are executed sequentially, in order, and process flow is blocked until completion.

Characteristics:

• Non-Blocking statements allow operating on “old” values, crucial for sequential logic.
• Blocking statements allow a sequence of operations on immediately updated values, more like software programming.

Rules for Signal Assignment

• Synchronous Sequential Logic: Use always @(posedge clk) and non-blocking assignments (<=).
• Simple Combinational Logic: Use continuous assignments (assign).
• More Complex Combinational Logic: Use always @ (*) and blocking assignments (=).
• No Multiple Assignments: Do not assign the same signal in more than one always block or in a continuous assignment.

What Did We Learn?

• Basics of describing sequential circuits in Verilog using always blocks, reg variables, sensitivity lists, and non-blocking assignments.
• The always statement for sequential and combinational logic.
• Blocking vs. Non-blocking statements and their appropriate use.
• Describing FSMs in Verilog with state registers, next state logic, and output logic.

Timing

What Will We Learn Today?

• Timing in combinational circuits:
  • Propagation delay and contamination delay.
  • Glitches.
• Timing in sequential circuits:
  • Setup time and hold time.
  • Determining how fast a circuit can operate.

Tradeoffs in Circuit Design

Circuit design involves balancing tradeoffs between:

• Area: Circuit area is proportional to cost.
• Speed / Throughput: Desired faster, more capable circuits.
• Power / Energy: Limited power supply in mobile devices, dissipation in high-performance devices.
• Design Time: Designers are expensive, and time-to-market is critical.

Circuit Timing

• Until now, we investigated logical functionality. Now we focus on timing.
• What about timing?
  • How fast is a circuit?
  • How can we make a circuit faster?
  • What happens if we run a circuit too fast?
• A logically correct design can still fail due to real-world implementation issues related to timing.

Part 1: Combinational Circuit Timing

Digital Logic Abstraction

• “Digital logic” is a convenient abstraction where output changes immediately with input.

Combinational Circuit Delay

• In reality, outputs are delayed from inputs due to finite switching time of transistors.

• Real Inverter Delay Example: Demonstrates actual delay in a real inverter circuit.

Circuit Delay and Its Variation

• Delay is fundamentally caused by capacitance and resistance in a circuit and the finite speed of light.
• Anything affecting these quantities can change delay:
  • Rising (0→1) vs. falling (1→0) inputs.
  • Different inputs have different delays.
  • Changes in environment (e.g., temperature).
  • Aging of the circuit.
• We have a range of possible delays from input to output.

Delays from Input to Output Y

• Contamination delay ($t_{cd}$): Delay until output Y starts changing.
• Propagation delay ($t_{pd}$): Delay until output Y finishes changing.

Calculating Longest & Shortest Delay Paths

• We care about both longest and shortest delay paths.
• Critical Path: Longest delay path determines the maximum operating frequency.
• Short Path: Shortest delay path is important for hold time constraints.

• Example Circuit and Delays:
  • Critical (Longest) Path: $t_{pd}=2t_{pd\_AND}+t_{pd\_OR}$
  • Shortest Path: $t_{cd}=t_{cd\_AND}$

Example $t_{pd}$ for a Real NAND-2 Gate

• Datasheet example showing how propagation delay ($t_{pd}$) varies with supply voltage and temperature for a 74HC00 NAND gate.

• Heavy dependence on voltage and temperature.

Disclaimer: Calculating Long/Short Paths

• It’s not always easy to determine long/short paths.
  • Not all input transitions affect the output.
  • Multiple different paths from input to output.
• In reality, circuits are not all built equally.
  • Different instances of the same gate have different delays.
  • Wires have nonzero delay.
  • Temperature/voltage affect circuit speeds, potentially changing the critical path.
• Designers assume “worst-case” conditions and use statistical simulations.

Combinational Timing Summary

• Circuit outputs change some time after inputs change.
• Delay is dependent on inputs, environmental state, etc.
• Range of possible delays characterized by:
  • Contamination delay ($t_{cd}$): minimum possible delay.
  • Propagation delay ($t_{pd}$): maximum possible delay.
• Delays change with circuit design and operating conditions.

Output Glitches

Glitches

• Glitch: One input transition causes multiple output transitions.

• Circuit Example: AND-OR-NOT gate configuration showing how a single input transition can cause a glitch due to different path delays.

• Optional: Avoiding Glitches Using K-Maps:

  • Glitches are visible in K-maps, occurring when moving between prime implicants.
  • Adding a consensus term can fix glitches by ensuring no transition between different prime implicants.

• Avoiding Glitches - Q: Do we always care about glitches?
  • Fixing glitches is undesirable: more area, power, design effort.
  • The circuit eventually converges to the right value regardless of glitches.
  • A: No, not always! If we only care about the long-term steady state output, we can safely ignore glitches. Designer must decide if glitches matter in their application.

Part 2: Sequential Circuit Timing

D Flip-Flop

Flip-flop samples D at the active clock edge and outputs the sampled value to Q, “storing” it until the next active clock edge.

D Flip-Flop Input Timing Constraints

D must be stable when sampled (at active clock edge).

• Setup time ($t_{setup}$): Time before the clock edge that data must be stable.
• Hold time ($t_{hold}$): Time after the clock edge that data must be stable.
• Aperture time ($t_a$): Time around the clock edge that data must be stable ($t_a=t_{setup}+t_{hold}$).

Violating Input Timing: Metastability

If D is changing when sampled, metastability can occur.

• Flip-flop output gets stuck somewhere between ‘1’ and ‘0’.
• Output eventually settles non-deterministically.

Flip-Flop Output Timing

• Contamination delay clock-to-q ($t_{ccq}$): Earliest time after the clock edge that Q starts to change (unstable).
• Propagation delay clock-to-q ($t_{pcq}$): Latest time after the clock edge that Q stops changing (stable).

Sequential System Design

• Multiple flip-flops are connected with combinational logic.
• Clock runs with period $T_c$ (cycle time).

Ensuring Correct Sequential Operation

• Need to ensure correct input timing on R2 (second flip-flop).

• Specifically, D2 must be stable at least $t_{setup}$ before and $t_{hold}$ after the clock edge.

• There is both a minimum and maximum delay between two flip-flops.

  • Combinational logic (CL) too fast → R2 $t_{hold}$ violation.
  • CL too slow → R2 $t_{setup}$ violation.

Setup Time Constraint

• Safe timing depends on the maximum delay from R1 to R2.
• Input to R2 must be stable at least $t_{setup}$ before the clock edge.

$T_c>t_{pcq}+t_{pd}+t_{setup}$

• Overall design performance is determined by the critical path $t_{pd}$.
  • Determines the minimum clock period (maximum operating frequency).
  • If the critical path is too long, the design will run slowly.
  • If the critical path is too short, each cycle will do very little useful work, wasting time in sequencing overhead.

Hold Time Constraint

• Safe timing depends on the minimum delay from R1 to R2.
• D2 must be stable for at least $t_{hold}$ after the clock edge.

$t_{ccq}+t_{cd}>t_{hold}$ $t_{cd}>t_{hold}-t_{ccq}$

• Hold time constraint does NOT depend on $T_c$.
• Very hard to fix $t_{hold}$ violations after manufacturing – must modify circuits!

Clock Skew

• To make matters worse, clocks have delay too! Clock does not reach all parts of the chip at the same time.
• Clock skew: Time difference between two clock edges.

• Clock Skew Example: Spatial distribution of clock skew in the Alpha 21264 processor.

Setup Time Revisited

• Safe timing requires considering the worst-case skew.
• Clock arrives at R2 before R1, leaving less time for combinational logic.

$T_c>t_{pcq}+t_{pd}+t_{setup}+t_{skew}$

Hold Time Revisited

• Safe timing requires considering the worst-case skew.
• Clock arrives at R2 after R1, increasing the minimum required delay for combinational logic.

$t_{cd}+t_{ccq}>t_{hold}+t_{skew}$

Clock Skew: Summary

• Skew effectively increases both $t_{setup}$ and $t_{hold}$, increasing sequencing overhead and reducing useful work per cycle.
• Designers must keep skew to a minimum with intelligent “clock networks” to ensure the clock arrives at all locations at roughly the same time.

Continue here: 06.5 Verification & Testing